This invention relates to a phase-locked circuit for use in responding to a sequence of input sample signals to produce a sequence of output sample signals phase-locked with the input sample signals.
A conventional phase-locked circuit of the type described has been usually implemented by a phase-locked loop (PLL) circuit which comprises a phase comparator (namely, a mixer), a low pass filter (LPF), and a voltage controlled oscillator (VCO). With this structure, the mixer is supplied with a sequence of input sample signals carried by an input carrier frequency together with a local carrier signal generated by the voltage controlled oscillator. The local carrier signal has a local carrier frequency. The mixer produces a phase difference signal representative of a phase difference between the input carrier frequency and the local carrier frequency. The phase difference signal is filtered by the low pass filter into a filtered difference signal and is thereafter sent to the voltage controlled oscillator. As a result, a phase of the local carrier signal is controlled so as to be phase-locked with a phase of the input carrier signal in accordance with the phase difference in the voltage controlled oscillator.
Herein, it often happens that the filtered difference signal includes a frequency component such that the frequency component falls outside of a pull-in range of the phase-locked loop circuit. In this event, the phase-locked loop circuit is put into an inactive state. In other words, a phase lock operation can not be accomplished in the conventional phase-locked loop circuit as long as the filtered difference signal does not fall within the pull-in range. This means that the phase-locked loop circuit can be put in an asynchronous state while the local carrier frequency is not close to the input carrier frequency. This makes a quick phase lock operation difficult and brings about retardation of the phase lock operation.
Recently, consideration is made about a digital phase-locked circuit which carries out a phase lock operation by digitally processing input complex sample signals each of which is divisible into a real component and an imaginary component orthogonal to the real component. In this event, only one of the real and the imaginary components is derived from the input complex sample signal and is successively sent from a mixer to an integrator through an adder. The integrator is formed by a delay unit which delays each imaginary component by a single sample period to produce a delayed component which is fed back to the adder to be added to the following component on one hand and which is also fed back to the mixer to be mixed with the following imaginary component. With this structure, it is possible to carry out a phase lock operation like in the conventional phase-locked loop circuit which comprises the voltage controlled oscillator, as mentioned above.
However, a long time is also required in the digital phase-locked circuit until a phase-locked state is accomplished.